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DS2401 Silicon Serial Number
www.dalsemi.com
FEATURES
Upgrade and drop-in replacement for DS2400 - Extended 2.8 to 6.0 voltage range - Multiple DS2401s can reside on a common 1-Wire bus Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48bit serial number + 8-bit CRC tester); guaranteed no two parts alike Built-in multidrop controller ensures compatibility with other MicroLAN products 8-bit family code specifies DS2401 communications requirements to reader Presence Pulse acknowledges when the reader first applies voltage Low-cost TO-92, SOT-223 and TSOC surface mount packages Reduces control, address, data, and power to a single pin Zero standby power required Directly connects to a single port pin of a microprocessor and communicates at up to 16.3 kbits/s TO-92 tape & reel version with leads bent to 100 mil spacing (default) or with straight leads (DS2401T-SL) Applications - PCB Identification - Network Node ID - Equipment Registration Operates over industrial temperature range of -40C to +85C
PIN ASSIGNMENT
TO-92
DALLAS DS2401
TSOC PACKAGE
TOP VIEW 3.7 X 4.0 X 1.5 mm
123
123
TOP VIEW See Mech. Drawings Section
BOTTOM VIEW
PIN DESCRIPTION
Pin 1 Pin 2 Pin 3 Pin 4 Pin 5-6 TO-92/SOT-223 Ground Data (DQ) No Connect Ground - TSOC Ground Data (DQ) No Connect No Connect No Connect
ORDERING INFORMATION
DS2401 DS2401Z DS2401T DS2401T-SL DS2401Y DS2401P DS2401V DS2401X1 TO-92 Package SOT-223 Surface Mount Package Tape & Reel of DS2401 Like DS2401T but straight leads Tape & Reel of DS2401Z TSOC Surface Mount Package Tape & Reel of DS2401P Chip Scale Pkg., Tape & Reel
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DESCRIPTION
The DS2401 enhanced Silicon Serial Number is a low-cost, electronic registration number that provides an absolutely unique identity which can be determined with a minimal electronic interface, typically a single port pin of a microcontroller. The DS2401 consists of a factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (01h). Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. Power for reading and writing the device is derived from the data line itself with no need for an external power source. The DS2401 is an upgrade to the DS2400. The DS2401 is fully reverse-compatible with the DS2400 but provides the additional multi-drop capability that enables many devices to reside on a single data line. The familiar TO-92, SOT-223 or TSOC package provides a compact enclosure that allows standard assembly equipment to handle the device easily.
OPERATION
The DS2401' internal ROM is accessed via a single data line. The 48-bit serial number, 8-bit family s code and 8-bit CRC are retrieved using the Dallas 1-Wire protocol. This protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. All data is read and written least significant bit first.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master system and one or more slaves. In all instances, the DS2401 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing). For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3-state outputs. The DS2401 is an open drain part with an internal circuit equivalent to that shown in Figure 2. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figure 3. The value of the pullup resistor should be approximately 5 k for short line lengths. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3 kbits per second. The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset.
DS2401 MEMORY MAP Figure 1
8-Bit CRC Code MSB LSB MSB 48-Bit Serial Number LSB 8-Bit Family Code (01h) MSB LSB
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DS2401 EQUIVALENT CIRCUIT Figure 2
BUS MASTER CIRCUIT Figure 3
A) Open Drain
To data connection of DS2401
B) Standard TTL
To data connection of DS2401
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TRANSACTION SEQUENCE
The sequence for accessing the DS2401 via the 1-Wire port is as follows: Initialization ROM Function Command Read Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a Presence Pulse(s) transmitted by the slave(s). The Presence Pulse lets the bus master know that the DS2401 is on the bus and is ready to operate. For more details, see the "1-Wire Signaling" section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 4):
Read ROM [33h] or [0Fh]
This command allows the bus master to read the DS2401' 8-bit family code, unique 48-bit serial s number, and 8-bit CRC. This command can only be used if there is a single DS2401 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). The DS2401 Read ROM function will occur with a command byte of either 33h or 0Fh in order to ensure compatibility with the DS2400, which will only respond to a 0Fh command word with its 64-bit ROM data.
Match ROM [55h] / Skip ROM [CCh]
The complete 1-Wire protocol for all Dallas Semiconductor iButtons contains a Match ROM and a Skip ROM command. (See the Book of DS19xx iButton Standards). Since the DS2401 contains only the 64-bit ROM with no additional data fields, the Match ROM and Skip ROM are not applicable and will cause no further activity on the 1-Wire bus if executed. The DS2401 does not interfere with other 1-Wire parts on a multidrop bus that do respond to a Match ROM or Skip ROM (for example, a DS2401 and DS1994 on the same bus).
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example.
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1-WIRE SIGNALING
The DS2401 requires a strict protocol to ensure data integrity. The protocol consists of four types of signaling on one line: reset sequence with Reset Pulse and Presence Pulse, write 0, write 1 and read data. All these signals except Presence Pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2401 is shown in Figure 5. A reset pulse followed by a Presence Pulse indicates the DS2401 is ready to send or receive data given the correct ROM command. The bus master transmits (TX ) a reset pulse (tRSTL , minimum 480 s). The bus master then releases the line and goes into receive mode (RX ). The 1-Wire bus is pulled to a high state via the 5 k pullup resistor. After detecting the rising edge on the data pin, the DS2401 waits (tPDH, 15-60 s) and then transmits the Presence Pulse (tPDL , 60-240 s).
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS2401 to the master by triggering a delay circuit in the DS2401. During write time slots, the delay circuit determines when the DS2401 will sample the data line. For a read data time slot, if a "0" is to be transmitted, the delay circuit determines how long the DS2401 will hold the data line low overriding the "1" generated by the master. If the data bit is a 1, the DS2401 will leave the read data time slot unchanged.
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ROM FUNCTIONS FLOW CHART Figure 4
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INITIALIZATION PROCEDURE "RESET AND PRESENCE PULSES" Figure 5
RESISTOR MASTER DS2401
480 s tRSTL < * 480 s tRSTH < (includes recovery time) 15 s tPDH < 60 s 60 s tPDL < 240 s
In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 s.
READ/WRITE TIMING DIAGRAM Figure 6 Write-One Time Slot
RESISTOR MASTER
60 s tSLOT < 120 s 1 s tLOW1 < 15 s 1 s tREC <
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READ/WRITE TIMING DIAGRAM (cont' Figure 6 d) Write-zero Time Slot
60 s tLOW0 < tSLOT < 120 s 1 s tREC <
Read-data Time Slot
RESISTOR MASTER DS2401
60 s tSLOT < 120 s 1 s tLOWR < 15 s 0 tRELEASE < 45 s 1 s tREC < tRDV = 15 s tSU < 1s
CRC GENERATION
To validate the data transmitted from the DS2401, the bus master may generate a CRC value from the data as it is received. This generated value is compared to the value stored in the last 8 bits of the DS2401. If the two CRC values match, the transmission is error-free. The equivalent polynomial function of this CRC is: CRC = x8 + x5 + x4 + 1. For more details, see the Book of DS19xx iButton Standards.
CUSTOM DS2401
Customization of a portion of the unique 48-bit serial number by the customer is available. Dallas Semiconductor will register and assign a specific customer ID in the 12 most significant bits of the 48-bit field. The next most significant bits are selectable by the customer as a starting value, and the least significant bits are non-selectable and will be automatically incremented by one. Certain quantities and conditions apply for these custom parts. Contact your Dallas Semiconductor sales representative for more information. 8 of 10 102199
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ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.5V to +7.0V -40 to +85 C C -55 to +125 C C 260 for 10 seconds C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Logic 1 Logic 0 Output Logic Low @ 4 mA Output Logic High Input Load Current Operating Charge SYMBOL VIH VIL VOL VOH IL QOP MIN 2.2 -0.3
(-40 to +85 VPUP =2.8V to 6.0V) C C;
TYP MAX VCC +0.3 +0.8 0.4 6.0 30 UNITS V V V V A nC NOTES 1,6 1 1 1,2 3 7,8
VPUP 5
CAPACITANCE
PARAMETER I/O (1-Wire) SYMBOL CIN/OUT MIN TYP MAX 800
(tA = 25 C)
UNITS pF NOTES 9
AC ELECTRICAL CHARACTERISTICS
PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 60 1 60 0 1 480 480 15 60
(-40C to +85C; VPUP =2.8V to 6.0V)
TYP MAX 120 15 120 45 1 UNITS s s s s s s s s s s s NOTES
exactly 15 15
5 4 10
60 240
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NOTES:
1. All voltages are referenced to ground. 2. VPUP = external pullup voltage. 3. Input load is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum (15 s total from falling edge on 1-Wire bus). 6. VIH is a function of the external pullup resistor and the VCC supply. 7. 30 nanocoulombs per 72 time slots @ 5.0V. 8. At VCC =5.0V with a 5 k pullup to VCC and a maximum time slot of 120 s. 9. Capacitance on the I/O pin could be 800 pF when power is first applied. If a 5 k resistor is used to pullup the I/O line to VCC, 5 s after power has been applied the parasite capacitance will not affect normal communications. 10. The reset low time (tRSTL) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise it could mask or conceal interrupt pulses if this device is used in parallel with a DS2404 or DS1994.
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